1. Field of the Invention
The present invention generally relates to wiring systems for integrated circuits (IC) and, more particularly, to wiring systems which facilitate engineering changes for the following functions: electrical characterization; diagnostic testing; and circuit modifications for repair or evaluation. These functions may hereinafter be collectively referred to as Engineering Changes or EC's.
2. Description of the Prior Art
The formation of integrated circuit chips in accordance with different technologies has been known for a number of years. A demand for increased complexity of electronic systems including such integrated circuits has caused the development of techniques for wiring modification and repair of such IC chips.
The IC multi-layer construction is similar to multi-layer circuit boards in that wiring can be run in a direction parallel to the surface at the interface between any two dielectric layers. Wiring can be run perpendicular to the surface and between wiring layers with through-holes or "vias" in the layers which are selectively filled with conductive materials. Multi-layer wiring and modules have been implemented with a variety of technologies including multi-layered co-fired ceramics, silicon based thin film structures, ceramic based thin film structures and combinations of those techniques.
However, because of the multi-layer construction, there is no ready access to wiring other than on the surface of the multi-layer structure. Therefore, engineering changes cannot readily be made.
Perhaps of equal importance is the fact that while electronic modules are large relative to the chips they contain, they are often very complex and of fairly small overall dimensions. Therefore, they are subject to connector or conductor defects in the same manner as the chips to be mounted thereon and so manufacturing yields of the multi-layer structure must also be considered. The length of the conductors is quite substantial because complex wiring metallization must be provided to allow each output terminal of one chip to be connected to a plurality of other input terminals on other chips. Additionally, so-called fanout wiring is often provided to interface between the fine wiring patterns characteristic of the connector spacing of the chips and the relatively more coarse wiring patterns on multi-chip modules (MCM). The problem of circuit defects is aggravated by the manufacturing processes used to create the multi-layer structures, which are difficult to characterize, diagnose, or effect repairs.
Since such structures are complex and require a number of processing steps for each layer, substantial expense is involved in fabrication of the multi-layer structure. It is therefore economically important that the multi-layer module be repairable. It is similarly important that diagnostics are conducted, design changes are possible, or circuit repairs are possible on IC's to ensure corrective masks used in the IC fabrication are effective. In the past, this has been accomplished on modules by a process known as ECing or the implementing of engineering changes, which required providing one or more layers of redistribution wiring from the I/O pads to EC pads on the top surface. However, these layers of redistribution wiring are also subject to the same potential defects as other wiring layers and are not repairable. Further, such patterns of redistribution wiring are in close proximity to each other, requiring high line (e.g., wiring patterns) quality, and, parasitic capacitance will exist causing signal delays, reduced noise margins and other effects, thereby posing a severe restriction on wiring design rules. Additionally, in order to facilitate engineering changes for the following functions: electrical characterization; diagnostic testing; and circuit modifications for repair or evaluation, a significant amount of product and process complexity is required. This function also traditionally requires additional area for the redistribution wiring and EC pads, thus limiting the maximum possible density of the wiring.
Within the individual IC chip, the complexity of the problem is further complicated because electrical access to internal circuit nodes must be accomplished on an extremely small scale. However, such access to an integrated circuit is often necessary in order to characterize the electrical behavior of the node, electrically stimulate the node, or to establish continuity between the node and some other circuit node or access point for EC purposes. These exercises are done in failure analysis, characterization, and design debug environments to address business needs.
The need to electrically establish continuity between the node of interest and a pad, test point, or circuit node that is substantially distant is increasing. This is often driven by the need to bring out a node of interest to a location where it is not obstructed by the packaging, probe equipment, or other chip surface features for characterization purposes. Additionally, the rerouting of circuit nets for engineering changes may require substantial lengths of wiring between nodes to be linked.
The EC's of internal circuit nodes for initial design verification/debug or failure analysis has been addressed in the past by opening an access point to the circuit node of interest with blanket delayering, localized delayering or focused-ion-beam (FIB) milling techniques, the optional depositions of a conductive pad or line using FIB, laser chemical vapor deposition (LCVD), or conventional IC processing techniques, and possibly followed with the probing of the exposed node or deposited pad using contact probing or electron-beam probing approaches.
An early approach to electrically access internal nodes involved using lithography techniques in a laboratory setting to pattern a mask used to define regions where holes would be etched down to the circuit nodes of interest. Subsequent to this preparation of the chip, mechanical probes were used to make contact to the exposed circuit nodes. In time, electron-beam probes were used for the interrogation or stimulation of these nodes; e.g., voltage contrast and electron beam induced current techniques. This approach worked well for devices patterned with up to two levels of wiring and where the input/output pads to the device were located around the perimeter of the chip leaving most of the chip circuitry exposed even when probe cards were used to electrically stimulate the chip circuitry.
As additional levels of wiring were added to integrated circuit designs, the former technique of etching holes to the underlying circuit nodes lost its effectiveness due to poor aspect ratios of the etched holes. FIB approaches offered the high aspect ratio feature needed and are currently widely used to access circuit nodes. Additionally, many circuit designers have brought key circuit nodes up to test points at the upper levels of wiring in their initial hardware designs to facilitate the electrical access to these nodes.
FIB techniques are also widely used today for circuit modifications for engineering changes which are incorporated herein by reference to the article entitled "Design Guidelines for FIB Modifiability and a Case Study of High Performance SCSI Chip with Timing Problems" by S. X. Li et al, published in the Proceedings of the 20th International Symposium for Testing and Failure Analysis, Nov. 13-18, 1994. However, this approach is limited to placement of spare metal lines. FIB deposited lines contain a very high impurity concentration (e.g., carbon) and for typical line widths, lengths exceeding 50 microns may pose a problem due to high resistance (typically around 500 milliohms per square). Long FIB deposited lines also require a lengthy deposition time. A current practice to address this problem is to use an LCVD metal deposition technique to deposit the bulk of the line segment along with shorter elements of FIB deposited lines to complete the net. Additionally, semiconductor manufacturers are designing in spare wires at the upper levels of metal for the potential future use for circuit modifications.
The various approaches used in the past have a number of disadvantages; namely:
1. Wires must be placed (manually or through some sort of automated "fill" tool) during the design layout phase; PA1 2. If left floating, the spare wires are susceptible to electrostatic charging problems; PA1 3. Random placement of the spare wires makes it difficult for an analyst to locate them, especially if a stud via technology is used eliminating any features that would distinguish the spare wires from functional wires; and, PA1 4. Such wires have no function unless used for a circuit change. PA1 5. No facility is offered for external electrical access through chip pads to internal circuit nodes, for characterization and diagnostics purposes.
An example of prior art module wiring schemes which allow some degree of repairs and engineering changes to be made is described in U.S. Pat. No. 4,489,364 to Chance et al which shows an electronic circuit module in which connections to pads to which chips are connected are buried within the body of the multi-layer structure but are periodically brought to the surface of the module and linked by EC pads of a so-called "dog-bone" shape. Continuity of these connections may be broken by severing the narrow portion of the dog-bone and EC connections may be made thereto either with or without severing the original connection. However, if a defect occurs in or between the C4 pad and the first EC pad, no repair is possible and the module must be discarded. The wiring through via holes is particularly vulnerable to the occurrence of discontinuities, as well, which may or may not be repairable and, in any event, repair would require point-to-point wiring over a considerable distance, further increasing parasitic impedance of the overall wiring system. It can also be readily appreciated that the length of wiring involved in this scheme, including the repeated vertical traversals of the multi-layer structure through vias, is large and has a large lumped capacitance.
Additionally, U.S. Pat. No. 4,746,815 to Bhatia et al provides a switching circuit within the module to allow sharing of EC pads between received and driver circuits. U.S. Pat. No. 4,453,176 to Chance et al shows wiring to capacitances buried within the multi-layer structure. U.S. Pat. No. 4,840,924 to Kinbara shows a particular structure for the dog-bone EC pads. U.S. Pat. No. 4,254,445 to Ho shows a staggered chip location arrangement for a large number of chips in a module to minimize potential wiring crossovers and maximize the number of EC pads which can be provided. U.S. Pat. No. 4,549,200 to Ecker et al shows a repairable multi-level overlay system using redistribution. U.S. Pat. No. 4,546,413 to Feinberg et al shows a module structure in which EC pads are provided on both major surfaces of the multi-layer structure. U.S. Pat. No. 4,706,165 to Takenaka et al shows a multi-layer structure in which connections to module connection pins are made through vias to EC pads at the upper surface of the module to increase the types of engineering changes and repairs which can be made. U.S. Pat. No. 5,155,577 to Chance et al shows a connection matrix between terminals of IC carrier and EC pads. U.S. Pat. No. 5,243,140 to Bhatia et al shows a wiring system on the top surface of a multiple chip module which includes a redistribution layer. U.S. Pat. No. 5,508,938 to Wheeler shows special interconnect layer employing offset trace layout for advanced multi-chip module packages using conventional EC approach. U.S. Pat. No. 5,214,250 to Cayson et al shows a method of reworking circuit panels which can overlay encapsulated replacement lines one on top of another.